1. Field of the Invention
The invention relates generally to channel stress within field effect devices. More particularly, the invention relates to stress liners that influence channel stress within field effect devices.
2. Description of the Related Art
Historically, most performance improvements in semiconductor field effect transistor (FET) devices have been realized by a downward scaling of the relative dimensions of the devices. This trend is becoming increasingly more difficult to continue as the devices reach their physical scaling limits. As a consequence, advanced FETs and the complementary metal oxide semiconductor (CMOS) circuits in which they may be used, are increasingly utilizing strain engineering to achieve desired circuit performance.
Strain engineering relies on the observation that carrier mobility within a semiconductor channel of a field effect device may be increased by inducing a mechanical strain within the semiconductor channel of the field effect device. A predicted mobility enhancement will typically depend upon carrier type (i.e., a hole or an electron) and the magnitude and direction of an applied stress (i.e., one that induces a strain) in relation to a semiconductor channel crystal orientation and direction of current flow. In a (100) silicon semiconductor substrate channel, electron mobility is typically increased by a tensile strain in the current flow direction, so tensile strain should provide an improved n-channel FET (i.e., nFET) performance. Conversely, hole mobility is typically increased by a compressive strain in a current flow direction, so compressive strain should provide an improved p-channel FET (i.e., pFET) performance.
A stress liner, which is typically deposited as a blanket layer over an FET device after a source/drain silicide formation processing step when fabricating the FET device, is included among the most useful and cost effective structures for inducing a semiconductor channel strain within the FET device.
FIG. 1 shows a plurality of generic FETs 10 and 10′ that incorporate a corresponding plurality of stress liners 90 and 90′. The plurality of FETs 10 and 10′ comprises a plurality of well regions 20 and 20′ located over a substrate 9. The plurality of well regions 20 and 20′ further comprises corresponding source/drain regions 30 and 30′ that in turn are separated by corresponding semiconductor channel regions 40 and 40′ located aligned beneath a plurality of corresponding gate dielectrics 50 and 50′ having a corresponding plurality of gate electrodes 60 and 60′ located thereon.
Optionally, the plurality of FETs 10 and 10′ is separated by a plurality of isolation regions 70 that typically comprise a dielectric isolation material. Each of the individual gate electrodes 60 and 60′ typically has a corresponding dielectric sidewall spacer 80 or 80′ disposed thereupon. The dielectric sidewall spacers 80 or 80′ typically comprise an inner spacer comprising an oxide material and an outer spacer comprising a nitride material, absent stress. The plurality of stress liners 90 and 90′ typically comprise an appropriate tensile silicon nitride material or compressive silicon nitride material that covers the plurality of source/drain regions 30 and 30′, the plurality of sidewall spacers 80 and 80′, and the plurality of gate electrodes 60 and 60′.
For a given stress liner 90 or 90′ and a corresponding FET 10 or 10′ geometry, a semiconductor channel 40 or 40′ strain will typically scale with the stress of the stress liner material. The stress liners 90 and 90′ may comprise the same or different materials, and exhibit the same or different stresses. When FETs 10 and 10′ are both FETs or both pFETs, the stress liners 90 and 90′ would typically be formed from the same material; when the FETs 10 and 10′ comprise one nFET and one pFET, stress liners 90 and 90′ would typically be formed from a compressive stress material for the pFET and a tensile stress material for the nFET.
Silicon nitride is a particularly favored stress liner material for stress liners 90 and 90′. Silicon nitride stress liner materials typically exhibit excellent thermal stability and excellent dielectric properties, as well as desirable barrier properties, good adhesion, high modulus and ease of patterning. However, as gate pitch dimensions decrease, effectiveness of stress liners, including in particular silicon nitride stress liners, decreases. Thus, a need exists for more effective stress liners for use in CMOS structures having decreased dimensions, and in particular decreased gate pitch dimensions.
Various aspects of stress liners are disclosed in the semiconductor fabrication art.
For example, Cheng et al., in U.S. Pub. No. 2005/0186722 teaches a method for selectively relieving stress within a silicon nitride stress liner. The method uses a selective ion implantation of carbon or oxygen into a portion of the silicon nitride stress liner whose stress is desired to be modified and relieved.
In addition, Bryant et al., in U.S. Pub. No. 2005/0285187 teaches separate stress liners for an nFET device and a pFET device within a CMOS structure
Finally, Thompson et al., in “Future of Strained Si/Semiconductors in Nanoscale MOSFETS,” IEDM 2006, Paper 27.1, teaches in general maximum mobility enhancements that may be achieved for strained silicon substrates
Since channel stress is likely to continue to be of considerable importance as semiconductor technology, including in particular CMOS technology, advances, desirable are additional semiconductor structures, including in particular CMOS structures, that beneficially incorporate novel stress liners that provide enhanced performance.